The sensors thus produced with CMOS technology have the advantage of making it possible to produce on one and the same silicon integrated circuit microchip both the image sensor proper, that is to say in general a matrix of photosensitive points, and also complex image processing electronic circuits. This CMOS technology has the advantage moreover of consuming less energy than the older CCD technologies (charge transfer technology).
The simplest construction which has been devised for a pixel based on MOS transistors is represented schematically in FIG. 1; it is a pixel with three transistors and it comprises a photodiode PD receiving the light of the image, a readout transistor TL having its gate linked to the photodiode, a row selection transistor TS linked between the readout transistor and a column conductor COL so as to apply to the column conductor a potential representing the quantity of charge integrated in the photodiode, and a reset transistor TR linked to the photodiode for periodically dumping the charge generated on the photodiode.
The photodiode is exposed to light whereas the other elements are preferably masked by an opaque layer. The readout transistor TL has a follower transistor function: its gate is linked to the photodiode; its drain is linked to a power supply Vdd or a fixed voltage; its source copies the potential of the photodiode during the readout phase.
The row selection transistor TS is turned on solely during the readout phase for a determined row of pixels; its gate is for this purpose linked to a row conductor SEL common to all the pixels of this row. During the readout phase it links the source of the readout transistor to the column conductor COL which is common to all the pixels of one and the same column.
Layouts of pixels with four or five transistors have also been proposed, making it possible notably to globally acquire the whole of the image for a duration of exposure which not only is the same for all the image points (or pixels) but which begins at the same instant for all the pixels and terminates at the same instant, before commencing an operation for reading out the electronic charge engendered at each point by this exposure. These pixels with four or five transistors use intermediate storage, on a storage node situated in the pixel, of the charge accumulated on the photodiode; a transfer of the charge of the photodiode to the storage node is performed before undertaking a signal reading on a column conductor. Patent publication FR 2 855 326 gives an example of this.
A pixel with five transistors is represented in FIG. 2 as an electrical layout and in FIG. 3 in cross section. It comprises:                a photodiode PD1 (N-type diffused zone N1 covered by a P-type surface diffusion P1, the whole in a P-type substrate) able to accumulate photosensitive charge for a duration of exposure,        an N-type storage zone N2 able to receive and temporarily preserve the charge of the photosensitive zone,        a first transfer gate G1 (that may be considered to be the gate of a transistor T1) controlled by a transfer conductor TRA (common to the whole of the matrix) for enabling the transfer of charge from the photosensitive zone N1 to the storage zone N2,        a second transfer gate G2 (that may be considered to be the gate of a transistor T2) for enabling the dumping of charge from the photodiode PD1 to an exhaust drain which is an N-type region N0 linked to a power supply conductor Vdd common to the whole of the matrix; this gate G2 is controlled by a global-reset conductor GRST,        a third gate G3 (that may be considered to be the gate of a reset transistor T3) for enabling the dumping of the charge from the storage zone N2 to an exhaust drain which is an N-type region N3 linked to the power supply conductor Vdd; this dumping is controlled by a conductor RST common to a whole row of pixels,        a first follower MOS transistor T4 having its drain (N′3 which in practice consists of the same diffused region as N3) linked to the power supply conductor at the potential Vdd, and its gate G4 linked to the storage zone N2 in such a way that the potential of the source of the first MOS transistor T4 follows, when this transistor conducts a current, the variations of the potential of the storage zone,        a second MOS transistor T5 for enabling the conduction of current in the first MOS transistor T4, the drain of the second transistor being linked to the source N4 of the first, the source N5 of the second transistor being linked to a column conductor COL common to all the pixels of one and the same column, and the second transistor T5 having its gate G5 controlled by the conductor SEL for selecting a row of pixels.        
The matrix operates in the following manner for an image shot and a readout of this image:
a. Initial State:                at the outset, before a time t0 corresponding to the start of a new snapshot, all the row conductors RST, which have a reset control role, have been placed at the potential Vdd; all the storage zones N2 are at the potential Vdd; the row selection conductors SEL are grounded; the conductor GRST is grounded and the channels under the gates G2 are closed; the transfer conductor TRA is at ground potential;        
b. Reset Before a New Exposure Period:                a global-reset pulse can be applied at an initial instant to the conductor GRST, thereby opening all the potential barriers under the gates G2 and dumping the charge of the photodiodes of the whole matrix; the pulse is a pulse at the potential level Vdd; when it terminates, the potential barriers under the gates G2 are reclosed for the whole matrix; the photosensitive regions N1 are henceforth isolated and can accumulate charge as a function of the light which illuminates them; the storage zones N2 are isolated and charged to a reference potential which here is the supply potential Vdd;        
c. Exposure:                thereafter, the photosensitive zones gather and store, for all the pixels of the image, the charge photogenerated by exposure to light; the potential of the photosensitive zone dips in proportion to the illumination received on the pixel for the chosen exposure duration;        
d. End of Exposure:                a brief pulse, from an instant t1 to an instant t′1, is applied to the conductor TRA, and the duration of exposure terminates at the instant t′1; the pulse dumps the charge of the photosensitive zone N1 into the storage zone N2; the potential of the point N2 falls by a value which is proportional to the charge shed and which represents the illumination over the duration of exposure;        
e. Before Matrix Readout:                the storage zone N2 is isolated; its potential remains constant (to within the dark current) throughout the image readout phase, which readout is done row by row;        
f. Readout of a Row (Phase 1):                a row is read by turning on the transistor T5 and therefore the transistor T4 via the conductor SEL; the transistor T4 then behaves in voltage follower mode and carries its gate voltage over to its source, to within the shift VT corresponding to the conduction threshold of the transistor T4; the value of the potential of the zone N2, decreased by the threshold voltage VT, is carried over to the column conductor COL, through the transistors T4 and T5; the potential of the column conductor is stored, for example in a first capacitor of a sample-and-hold device at the column extremity, awaiting a new measurement of potential performed immediately after and intended to eliminate, by subtraction, the influence of the threshold voltage on the measurement;        
g. Readout of a Row (Phase 2):                the row conductor RST of the same row of pixels is activated, the zone N2 passes to the potential Vdd; the column potential takes the value Vdd decreased by the threshold voltage VT; next, this conductor is re-grounded; the potential of the column is then stored by a second capacitor of the sample-and-hold device; by subtracting this measurement from the measurement performed in step f, the unknown VT, which may vary from one pixel to another, is eliminated and an accurate evaluation is obtained of the potential of the zone N2, representing the illumination of the pixel;        
h. Readout of the Other Rows:                the potential of the row selection conductor SEL is returned to zero, isolating the column COL from this pixel, and another row is then read out.        
A pixel with four transistors would not comprise the transistor T2 but would operate globally in the same manner, with the exception of the fact that the resetting of the storage node N2 by the conductor RST would be done during a second pulse on the conductor TRA, turning on the transfer transistor T1 and thus dumping both the storage node and the photodiode.
It is understood that for these two types of pixels, each readout is done by differencing between a potential resulting from the resetting of the storage zone and a potential resulting from the illumination after this reset. A certain number of error factors such as the error on VT are therefore eliminated.
But not all sources of error are eliminated.
There is in particular a source of error in the fact that the reset transistor T3 engenders some noise. At the moment at which it is turned on, it has a non-zero resistance Ron to the passage of current, and this engenders noise. This noise represents the fact that the potential applied to the storage zone at this moment is not really Vdd but is a value which can fluctuate around Vdd. The fluctuation depends notably on the capacitance C of the storage node N2. This noise is generally called “kTC noise” or “thermal noise of the switches”, dependent on the absolute temperature T and the capacitance C; k is Boltzmann's constant. If it is expressed as electric charge, this noise is equal to (kTC)1/2. If this noise is evaluated in terms of number of electrons, it is noted that it is nearly equal to 400×(C)1/2, at 300K, the capacitance being expressed in picofarads; this value is not negligible relative to the numbers of useful electrons generated by low-level illumination.
The fluctuation in potential level is found on the readout transistor T5 and on the column conductor and it is not eliminated by the double sampling readout since it does not necessarily have the same value during the first sampling and during the resetting of the storage zone N2 since the noise kTC is noise with a temporal component.
To eliminate the risk of introducing kTC-type noise into the signal, the invention proposes that the storage region N2 be divided into two parts one of which, adjacent to the reset gate G3, is covered by a diffused or implanted region of the same type of conductivity as the substrate in which the photodiode is formed, this region being brought to the fixed potential of the substrate, and the other of which is not covered by such a region and is not adjacent to the reset gate. This fixes the potential level of the region N2 at the moment of reset at a value which depends only on technological parameters and which is not subject to kTC-type noise.